1. VHDL Overview and Concepts. - 1. 1 What is VHDL. - 1. 2 Level of Descriptions. - 1. 3 Methodology and Coding Style Requirements. - 1. 4 VHDL Types. - 1. 5 VHDL Object Classes. - 1. 6 Vhdl Design Units. - 1. 7 Compilation Elaboration Simulation. - 2. Basic Language Elements. - 2. 1 Lexical Elements. - 2. 2 Syntax. - 2. 3 Types and Subtypes. - 2. 4 File. - 2. 5 Attributes. - 2. 6 Aliases. - 3. Control Structures. - 3. 1 Expression Classification. - 3. 2 Control Structures. - 4. Drivers. - 4. 1 Resolution Function. - 4. 2 Drivers. - 4. 3 Ports. - 5. VHDL Timing. - 5. 1 Signal Attributes. - 5. 2 The Wait Statement. - 5. 3 Simulation Engine. - 5. 4 Modeling with Delta Time Delays. - 5. 5 Inertial / Transport Delay. - 6. Elements of Entity/Architecture. - 6. 1 Vhdl Entity. - 6. 2 Vhdl Architecture. - 7. Subprograms. - 7. 1 Subprogram Definition. - 7. 2 Subprogram Rules and Guidelines. - 7. 3 Subprogram Overloading. - 7. 4 Functions. - 7. 5 Resolution Function. - 7. 6 Operator Overloading. - 7. 7 Concurrent Procedure. - 8. Packages. - 8. 1 Package. - 8. 2 Package Textio. - 8. 3 Compilation Order. - 9. User Defined Attributes Specifications and Configurations. - 9. 1 Attribute Declarations. - 9. 2 User-Defined Attributes. - 9. 3 Specifications. - 9. 4 Configuration Specification. - 9. 5 Configuration Declaration. - 10. Functional Models and Testbenches. - 10. 1 FM/BFM Modeling. - 10. 2 Testbench Modeling. - 11. UART Project. - 11. 1 UART Architecture. - 11. 2 UART Testbench. - 12. Vital. - 12. 1 Vital. - 12. 2 Vital Features. - 12. 3 Vital Model. - 13. Design for Synthesis. - 13. 1 Synthesis Methodology. - 13. 2 Constructs for Synthesis. - 13. 3 Resource Sharing. - Appendix A: Vhdl?93 And Vhdl?87 Syntax Summary. - Appendix B: Package Standard. - Appendix C: Package Textio. - Appendix D: Package Std_Logic_1164. - Appendix E: Vhdl Predefined Attributes. Language: English