1 Introduction. - 1. 1 Power as a Design Constraint. - 1. 2 Organization of this Book. - References. - 2 Power Estimation. - 2. 1 Power Dissipation Model. - 2. 2 Switching Activity Estimation. - 2. 3 Summary. - References. - 3 A Power Estimation Method for Combinational Circuits. - 3. 1 Symbolic Simulation. - 3. 2 Transparent Latches. - 3. 3 Modeling Inertial Delay. - 3. 4 Power Estimation Results. - 3. 5 Summary. - References. - 4 Power Estimation for Sequential Circuits. - 4. 1 Pipelines. - 4. 2 Finite State Machines: Exact Method. - 4. 3 Finite State Machines: Approximate Method. - 4. 4 Results on Sequential Power Estimation Techniques. - 4. 5 Modeling Correlation of Input Sequences. - 4. 6 Summary. - References. - 5 Optimization Techniques for Low Power Circuits. - 5. 1 Power Optimization by Transistor Sizing. - 5. 2 Combinational Logic Level Optimization. - 5. 3 Sequential Optimization. - 5. 4 Summary. - References. - 6 Retiming for Low Power. - 6. 1 Review of Retiming. - 6. 2 Retiming for Low Power. - 6. 3 Experimental Results. - 6. 4 Conclusions. - References. - 7 Precomputation. - 7. 1 Subset Input Disabling Precomputation. - 7. 2 Complete Input Disabling Precomputation. - 7. 3 Combinational Precomputation. - 7. 4 Multiplexor-Based Precomputation. - 7. 5 Conclusions. - References. - 8 High-Level Power Estimation and Optimization. - 8. 1 Register Transfer Level Power Estimation. - 8. 2 Behavioral Level Synthesis for Low Power. - 8. 3 Conclusions. - References. - 9 Conclusion. - 9. 1 Power Estimation at the Logic Level. - 9. 2 Optimization Techniques at the Logic Level. - 9. 3 Estimation and Optimization Techniques at the RT Level. - References. Language: English